JTL9253

Product Uses and Application Scope

• Medical Ultrasound
• High-speed imaging
• Orthogonal and Diversity Radio Receivers
• Test equipment

Product Features

• 1.8V power supply operation
• Low Power: 110 mW per channel at 125 MSPS, with scalable power options.
• SNR = 74 dB (to Nyquist); SFDR = 90 dBc (to Nyquist)
• DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)
• Serial LVDS (ANSI-644, default) and low-power, low-signal options (similar to IEEE 1596.3)
• 650 MHz full-power analog bandwidth
• 2V p-p input voltage range
• Serial Port Control
• Full-chip and single-channel power-off mode
• Flexible drill bit positioning
• Built-in and custom digital test pattern generation
• Multi-chip synchronization and clock divider
• Programmable output clock and data alignment
• Programmable output resolution
• Standby mode

Functional block diagram  

Product Description

The JTL9253 is a four-channel, 14-bit analog-to-digital converter (ADC) operating at 80 MSPS, 105 MSPS, or 125 MSPS, featuring an on-chip sample-and-hold circuit. It is designed for low cost, low power consumption, compact size, and ease of use. With a conversion rate of up to 125 MSPS, this device has been optimized to deliver excellent dynamic performance and low power dissipation in applications where small package size is critical.
The ADC requires a 1.8 V supply and an LVPECL-/CMOS-/LVDS‑compatible sampling‑rate clock to operate at full performance. Many applications do not need external reference or driver components.
The ADC automatically multiplies the sampling‑rate clock by the appropriate LVDS serial data rate. It provides a Data Clock Output (DCO) for capturing data on the output and a Frame Clock Output (FCO) to signal the arrival of a new output byte. Single‑channel power‑down is supported; when all channels are disabled, power consumption typically remains below 2 mW. The ADC incorporates several features designed to maximize flexibility and minimize system cost, including programmable output clock and data alignment, as well as digital test‑pattern generation. Available digital test patterns include built-in deterministic and pseudo‑random sequences, along with custom user‑defined test patterns that can be loaded via the Serial Peripheral Interface (SPI). The JTL9253 is offered in a RoHS‑compliant 48‑lead LFCSP package and is specified for an industrial temperature range of –40°C to +85°C. This product is protected by Chinese patents.

Product Highlights

• It occupies minimal space. The four ADCs are integrated into a compact, space-saving package.
• Low power consumption of 110 mW per channel at 125 MSPS, with scalable power options.
• Pin-compatible with the JTL9633 12-bit quad-channel ADC.
• Easy to use. The Data Clock Output (DCO) operates at frequencies up to 500 MHz and supports Double Data Rate (DDR) operation.
• User flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.