AD9213

Product Uses and Application Scope

• Active jamming/anti-jamming
• Electronic Surveillance/Anti-Surveillance
• Radar
• Military communications
• Spectrum analyzer

Product Features

• NSD Level:
  -155 dBFS/Hz at 10 GSPS, with a 170 MHz analog input at -9 dBFS;
  -153 dBFS/Hz at 10 GSPS, with a -1 dBFS analog input at 170 MHz;
• SFDR: 70 dBFS at 10 GSPS, with a -1 dBFS, 1 GHz analog input.
• SFDR excluding H2 and H3 (worst other spur): 89 dBFS at 10 GSPS, input −1 dBFS, 1 GHz;
• Low power consumption: Typical value is <4.6 W at 10 GSPS;
• Integrated input driver (6.5 GHz –3 dB analog input bandwidth);
• 1.4 V peak-to-peak full-scale analog input, with a differential input impedance of 50 Ω;
• 16-channel JESD204B output (with line rates up to 16 Gbps), supporting multi-chip synchronization with an accuracy of one sample;
• DDC NCO synchronization already includes an integrated DDC;
• 16 configuration profile settings for fast frequency hopping;
• On-chip temperature sensor with rapid out-of-range detection for efficient automatic gain control;
• On-chip negative voltage generation;
• Low CER:<1×10`;
• 12 mm × 12 mm, 192‑pin FC‑BGA package

Standard

• General Specification and Number: GJB597B-2012 “General Specification for Semiconductor Integrated Circuits”
• Detailed Specification and Confirmation Number: Q/GC0143-2025 “Detailed Specification for the Semiconductor Integrated Circuit AD9213-JTL 12-bit 10 GSPS A/D Converter”
• Quality Grade: N1 Level

Product Description

The AD9213-JTL is a single-channel, 12-bit, 10 GSPS radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. This device supports high‑dynamic‑range frequency‑domain and time‑domain applications that require wide instantaneous bandwidth and low conversion error rate (CER). The AD9213-JTL features a 16‑lane JESD204B interface to enable maximum bandwidth capabilities.
The AD9213‑JTL delivers exceptional dynamic range and linearity while operating at a typical power consumption of less than 4.6 W. This device employs an interleaved pipeline architecture and incorporates proprietary calibration and randomization techniques that effectively suppress spurious signals generated during the interleaving process, integrating them into the noise floor. By combining on-chip dither injection with a real-time calibration mechanism, the AD9213‑JTL maintains outstanding spurious-free dynamic range across a wide range of input signal conditions.
For applications requiring lower instantaneous bandwidth, the AD9213‑JTL’s on‑chip digital signal processing (DSP) capabilities offer advantages by reducing the output data rate and the number of JESD204B lanes needed to support the device. This DSP path includes a digital downconverter (DDC) with a 48‑bit numerically controlled oscillator (NCO), followed by a VO digital decimation stage that supports selectable decimation rates with factors of two or three.
In fast frequency-hopping applications, the AD9213‑JTL’s NCO supports up to 16 configuration profiles and features an independent trigger input, enabling wide‑range monitoring of target frequencies while reducing the number of JESD204B lanes. The AD9213‑JTL also provides precise multi‑chip synchronization, including synchronization of numerically controlled oscillators.
This device is packaged in a 192-ball fine-pitch ball grid array (FC‑BGA) and operates over a junction temperature range of −55 °C to +105 °C. It can serve as a domestic replacement for the AD9213‑10GAD analog-to-digital converter from Analog Devices, Inc.

The functional block diagram of this product is shown in Figure 1.

Figure 1 Functional Block Diagram